The present invention relates generally to a phase-locked loop circuit and, more particularly, to a phase-locked loop circuit for providing phase synchronization between a first signal and a second signal in which system phase errors caused by the components in the phase-locked loop circuit are minimized to assure accurate phase synchronization of the two signals.
Phase-locked loop circuits are well-known in the art and are used in a variety of applications. Basically a phase-locked loop circuit includes a phase detector, a low pass filter and a voltage controlled oscillator. By controlling the phase of the oscillator output signal, the loop is capable of locking to, or synchronizing with, the phase of an incoming signal.
Phase-locked loop circuits are commonly used in digital data systems to provide a data clock locked in phase synchronization with data bits in a serial digital data stream, the data clock being phase-locked to either a separate input clock signal or to the data bits of the data stream itself. In general, a phase detector circuit compares input and clock signals and provides a control signal to a voltage-controlled oscillator (VCO) generating the clock signal. The control signal controls frequency and phase of the clock signal in such a manner that clock and input signals are locked in phase synchronization. Thus, input data streams containing consecutive ones or zeros are, in MFM code, distinguished by the positions of the data bits in the data cells, i.e., near the centers or the edges of the cells. Data clock must therefore be correctly phase synchronized to the data cells to allow ones and zeros to be distinguished to provide the proper decoded data output.
In U.S. Pat. No. 4,069,462, to D. Dunn, which patent is incorporated herein by reference, there is described a phase-locked loop which may be used in the data recovery system of a rotating magnetic disk drive unit. The loop produces a signal which is in phase synchronism with an input signal which may assume multiple, but integrally related, frequencies. The loop operates with a dual mode of operation wherein frequency capture is first achieved utilizing a suitably selected frequency detector circuit and phase capture is subsequently achieved utilizing a separate, suitably selected phase detector circuit. In the initial frequency capture mode, lock-in to the frequency of a suitably selected reference signal is provided by the frequency detector circuit which is utilized as part of a closed loop so as to bring a signal derived from a voltage controlled oscillator into frequency synchronization with the reference signal, the frequency of which has a known integral relationship to the multiple frequencies of the input signal. The loop is then switched to its second mode of operation utilizing a phase detector circuit as part of the same closed loop so as to bring the phase of a signal derived from the voltage controlled oscillator signal into synchronization with the phase of the input signal independently of the frequency which the latter signal assumes. This process provides only phase synchronization so that the phase lock-up time is predictable and data storage capacity is optimized.
Another example of a phase-locked loop for use in the data recovery system of a rotating magnetic disk drive unit is described in U.S. Pat. No. 4,191,976, to W. A. Braun, which patent is also incorporated herein by reference. In the Braun patent, the circuit includes a phase difference measuring circuit providing a first signal proportional to phase difference between input pulse train and clock pulse train, the signal having related discontinuities at the points of minimum and maximum phase difference between input and clock pulse trains. A second signal is generated representing a selected value of phase difference, the selected value being greater than the minimum phase difference and less than the maximum phase difference. First and second signals are then compared to provide a signal representing difference between the measured and selected values of phase difference. The comparison signal thereby avoids the discontinuities at minimum and maximum values of phase difference by representing phase relationship between input and clock pulse trains relative to the selected value of phase difference rather than to the maximum or minimum values.
In the past, very little attention has been paid to the problem of system phase errors in the phase-locked loop; that is, fixed or steady state phase errors produced by the various components used in the phase-locked loop. The principal reason for the lack of concern over this problem has been that the density of the data stored on the disk has been at levels, i.e. around 4040 bits per inch or cell periods of around 155 nanoseconds apart, wherein the bit cell is considerably larger than the system phase errors. Consequently, the system phase errors have very little effect on the data integrity. As the density of the data stored on the disk increases, however, the length of the bit cell relative to the system phase errors becomes more and more of a problem and as a result becomes a limiting factor in the amount of data that can actually be stored and accurately recovered. Thus, it can be appreciated, that in order to store data and retrieve it reliably at high density levels, such as around 6060 bits per inch or at cell periods of around 103 nanoseconds, a phase-locked loop is needed in which the system phase errors are minimized.
Accordingly, it is an object of this invention to provide a new and improved phase-locked loop.
It is another object of this invention to provide a phase-locked loop for use in the data recovery system of a magnetic disk drive unit.
It is still another object of this invention to provide a phase-locked loop for use in the data recovery system of a magnetic disk drive unit employing a phase encoded signal format.
It is yet still another object of this invention to provide a phase-locked loop for use in the data recovery system of a magnetic disk drive unit employing a phase encoded signal format in which system phase errors are minimized.
It is another object of this invention to provide a phase-locked loop for use in a data recovery system of a magnetic disk drive unit in which data can be accurately stored on the disk at density levels of 6060 bits per inch or cell periods of 103 nanoseconds, or higher, and then reliably recovered.
It is still another object of this invention to provide a technique for minimizing system phase errors in a phase-locked loop circuit which is simple, economical and highly reliable.
The present invention provides a phase-locked loop which accomplishes the above and other objects.